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Merge pull request #1 from mumbel/v850patterns

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initial V850 patterns
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Aleckaj 2020-03-02 10:49:24 +01:00 committed by GitHub
parent f317ada6a8 ab6112c56e
commit 17540d31a8
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65
Ghidra/Processors/V850/data/patterns/V850_patterns.xml Normal file
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<patternlist>
<patternpairs totalbits="48" postbits="32">
<prepatterns>
<data>01111111 00000000</data> <!-- jmp [lp] -->
</prepatterns>
<postpatterns>
<data>10...... 00000111 ...00001 ........</data> <!-- PREPARE list12, imm5 -->
<data>10...... 00000111 ...00011 ........</data> <!-- PREPARE list12, imm5, sp -->
<data>00000011 00011110 ........ ........</data> <!-- ADDI imm16, sp, sp -->
</postpatterns>
</patternpairs>
<patternpairs totalbits="64" postbits="48">
<prepatterns>
<data>01111111 00000000</data> <!-- jmp [lp] -->
</prepatterns>
<postpatterns>
<data>10...... 00000111 ...01011 ........ ........ .........</data> <!-- PREPARE list12, imm5, simm16 -->
<data>10...... 00000111 ...10011 ........ ........ .........</data> <!-- PREPARE list12, imm5, imm16 -->
</postpatterns>
</patternpairs>
<patternpairs totalbits="80" postbits="64">
<prepatterns>
<data>01111111 00000000</data> <!-- jmp [lp] -->
</prepatterns>
<postpatterns>
<data>10...... 00000111 ...11011 ........ ........ ......... ........ .........</data> <!-- PREPARE list12, imm5, imm32 -->
</postpatterns>
</patternpairs>
<patternpairs totalbits="64" postbits="32">
<prepatterns>
<data>01...... 00000110 ........ ........</data> <!-- DISPOSE imm5, list12, [reg1] -->
<data>11100000 00000111 01001010 00000001</data> <!-- FERET -->
<data>11100000 00000111 01001000 00000001</data> <!-- EIRET -->
<data>11100000 00000111 01000100 00000001</data> <!-- CTRET -->
</prepatterns>
<postpatterns>
<data>10...... 00000111 ...00001 ........</data> <!-- PREPARE list12, imm5 -->
<data>10...... 00000111 ...00011 ........</data> <!-- PREPARE list12, imm5, sp -->
<data>00000011 00011110 ........ ........</data> <!-- ADDI imm16, sp, sp -->
</postpatterns>
</patternpairs>
<patternpairs totalbits="80" postbits="48">
<prepatterns>
<data>01...... 00000110 ........ ........</data> <!-- DISPOSE imm5, list12, [reg1] -->
<data>11100000 00000111 01001010 00000001</data> <!-- FERET -->
<data>11100000 00000111 01001000 00000001</data> <!-- EIRET -->
<data>11100000 00000111 01000100 00000001</data> <!-- CTRET -->
</prepatterns>
<postpatterns>
<data>10...... 00000111 ...01011 ........ ........ .........</data> <!-- PREPARE list12, imm5, simm16 -->
<data>10...... 00000111 ...10011 ........ ........ .........</data> <!-- PREPARE list12, imm5, imm16 -->
</postpatterns>
</patternpairs>
<patternpairs totalbits="96" postbits="64">
<prepatterns>
<data>01...... 00000110 ........ ........</data> <!-- DISPOSE imm5, list12, [reg1] -->
<data>11100000 00000111 01001010 00000001</data> <!-- FERET -->
<data>11100000 00000111 01001000 00000001</data> <!-- EIRET -->
<data>11100000 00000111 01000100 00000001</data> <!-- CTRET -->
</prepatterns>
<postpatterns>
<data>10...... 00000111 ...11011 ........ ........ ......... ........ .........</data> <!-- PREPARE list12, imm5, imm32 -->
</postpatterns>
</patternpairs>
</patternlist>

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Ghidra/Processors/V850/data/patterns/patternconstraints.xml Normal file
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<patternconstraints>
<language id="V850:LE:32:default">
<patternfile>V850_patterns.xml</patternfile>
</language>
</patternconstraints>