mirror of
https://github.com/NationalSecurityAgency/ghidra
synced 2024-10-12 21:23:07 +00:00
GP-1790: Spec'd out new aarch64 and arm32 instructions up to v9
This commit is contained in:
ghidorahrex
ghidra1
parent
d539d5da59
commit
0175606ad4
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@ -4,7 +4,7 @@
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endian="little"
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size="64"
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variant="v8A"
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version="1.5"
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version="1.6"
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slafile="AARCH64.sla"
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processorspec="AARCH64.pspec"
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manualindexfile="../manuals/AARCH64.idx"
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@ -20,7 +20,7 @@
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instructionEndian="little"
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size="64"
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variant="v8A"
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version="1.5"
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version="1.6"
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slafile="AARCH64BE.sla"
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processorspec="AARCH64.pspec"
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manualindexfile="../manuals/AARCH64.idx"
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@ -716,6 +716,23 @@ is b_31=0 & b_2630=0x05 & Addr26
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goto Addr26;
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}
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# C6.2.27 BC.cond page C6-1192 line 70348 MATCH x54000010/mask=xff000010
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# CONSTRUCT x54000010/mask=xff000010 MATCHED 1 DOCUMENTED OPCODES
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# b_0031=01010100...................1....
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:bc^"."^BranchCondOp Addr19
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is b_2531=0x2a & o1=0 & Addr19 & o0=1 & br_cond_op=15 & BranchCondOp
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{
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goto Addr19;
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}
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:bc^"."^BranchCondOp Addr19
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is b_2531=0x2a & o1=0 & Addr19 & o0=1 & BranchCondOp
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{
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if (BranchCondOp) goto Addr19;
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}
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# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000
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# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0
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# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000
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@ -1843,6 +1860,51 @@ is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=1
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Rd_GPR64 = tmp;
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}
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# C6.2.68 CPYFP, CPYFM, CPYFE page C6-1262 line 73913 MATCH x19000400/mask=x3f20fc00
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# C6.2.69 CPYFPN, CPYFMN, CPYFEN page C6-1267 line 74246 MATCH x1900c400/mask=x3f20fc00
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# C6.2.70 CPYFPRN, CPYFMRN, CPYFERN page C6-1272 line 74579 MATCH x19008400/mask=x3f20fc00
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# C6.2.79 CPYFPWN, CPYFMWN, CPYFEWN page C6-1317 line 77576 MATCH x19004400/mask=x3f20fc00
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# CONSTRUCT x19000400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
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cpyPhase:"p" is opt=0 {export 0:1;}
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cpyPhase:"m" is opt=1 {export 1:1;}
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cpyPhase:"e" is opt=2 {export 2:1;}
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cpyType: "" is b_1015=0x01 {export 0x01:1; }
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cpyType: "n" is b_1015=0x31 {export 0x31:1; }
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cpyType: "rn" is b_1015=0x21 {export 0x21:1; }
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cpyType: "wn" is b_1015=0x11 {export 0x11:1; }
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cpyType: "rt" is b_1015=0x09 {export 0x09:1; }
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cpyType: "rtn" is b_1015=0x39 {export 0x39:1; }
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cpyType: "rtrn" is b_1015=0x29 {export 0x29:1; }
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cpyType: "rtwn" is b_1015=0x19 {export 0x19:1; }
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cpyType: "t" is b_1015=0x0d {export 0x0d:1; }
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cpyType: "tn" is b_1015=0x3d {export 0x3d:1; }
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cpyType: "trn" is b_1015=0x2d {export 0x2d:1; }
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cpyType: "twn" is b_1015=0x1d {export 0x1d:1; }
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cpyType: "wt" is b_1015=0x03 {export 0x03:1; }
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cpyType: "wtn" is b_1015=0x33 {export 0x33:1; }
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cpyType: "wtrn" is b_1015=0x23 {export 0x23:1; }
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cpyType: "wtwn" is b_1015=0x13 {export 0x13:1; }
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define pcodeop MemoryCopyForward;
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# Memory Copy Forward-only
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:cpyf^cpyPhase^cpyType [Rd_GPR64]!, [Rs_GPR64]!, Rn_GPR64^"!"
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is size.ldstr & b_2429=0x19 & opt != 3 & cpyPhase & b_2121=0 & Rs_GPR64 & cpyType & Rn_GPR64 & Rd_GPR64
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{
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MemoryCopyForward(Rd_GPR64, Rs_GPR64, Rn_GPR64, cpyType, cpyPhase);
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}
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define pcodeop MemoryCopy;
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:cpy^cpyPhase^cpyType [Rd_GPR64]!, [Rs_GPR64]!, Rn_GPR64^"!"
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is size.ldstr & b_2429=0x1d & opt != 3 & cpyPhase & b_2121=0 & Rs_GPR64 & cpyType & Rn_GPR64 & Rd_GPR64
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{
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MemoryCopy(Rd_GPR64, Rs_GPR64, Rn_GPR64, cpyType, cpyPhase);
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}
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# C6.2.59 CRC32B, CRC32H, CRC32W, CRC32X page C6-611 line 35802 KEEPWITH
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# sf == 0 && sz = 00 CRC32CB variant
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@ -2257,7 +2319,20 @@ is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CR
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# AUNIT --inst xd503309f/mask=xfffff0ff --status nodest
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:dsb CRm_dbarrier_op
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is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=4 & Rt=0x1f
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is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10=2 & Op2=4 & Rt=0x1f
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{
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types:1 = 0x3; #MBReqTypes_All
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domain:1 = CRm_32;
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DataSynchronizationBarrier(domain, types);
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}
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# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503323f/mask=xfffff3ff
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# CONSTRUCT xd503323f/mask=xfffff3ff MATCHED 1 DOCUMENTED OPCODES
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# xd503323f/mask=xfffff3ff NOT MATCHED BY ANY CONSTRUCTOR
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# b_0031=11010101000000110011..1000111111
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:dsb CRm_32
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is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=1 & Rt=0x1f
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{
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types:1 = CRm_10;
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domain:1 = CRm_32;
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@ -5238,6 +5313,7 @@ is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x3 & Rn_G
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Rd_GPR64 = tmp_1;
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}
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# C6.2.271 SETF8, SETF16 page C6-1759 line 103584 MATCH x3a00080d/mask=xffffbc1f
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# CONSTRUCT x3a00080d/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES
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@ -5261,6 +5337,38 @@ is b_1531=0b00111010000000000 & b_14=1 & b_1013=0b0010 & b_0004=0b01101 & aa_Wn
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OV = (((aa_Wn >> 15) & 1) ^ ((aa_Wn >>16) & 1)) == 1;
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}
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# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00
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# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00
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# CONSTRUCT x1dc00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
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setPhase:"p" is b_1415=0 {export 0:1;}
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setPhase:"m" is b_1415=1 {export 1:1;}
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setPhase:"e" is b_1415=2 {export 2:1;}
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setType: "" is b_1013=0x1 {export 1:1; }
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setType: "n" is b_1013=0x9 {export 9:1; }
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setType: "t" is b_1013=0x5 {export 5:1; }
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setType: "tn" is b_1013=0xd {export 13:1; }
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define pcodeop memorySetTag;
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:setg^setPhase^setType [Rd_GPR64]!, Rn_GPR64!, Rs_GPR64
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is size.ldstr & b_2129=0xee & Rs_GPR64 & b_1415 <3 & setPhase & setType & Rn_GPR64 & Rd_GPR64 {
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memorySetTag(Rd_GPR64, Rn_GPR64, Rs_GPR64, setPhase, setType);
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}
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# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00
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# CONSTRUCT x19c00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
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define pcodeop memorySet;
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:setp^setPhase^setType [Rd_GPR64]!, Rn_GPR64!, Rs_GPR64
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is size.ldstr & b_2129=0xce & Rs_GPR64 & b_1415 <3 & setPhase & setType & Rn_GPR64 & Rd_GPR64 {
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memorySet(Rd_GPR64, Rn_GPR64, Rs_GPR64, setPhase, setType);
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}
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# C6.2.280 SEV page C6-1796 line 106224 MATCH xd503209f/mask=xffffffff
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# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
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# CONSTRUCT xd503209f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
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@ -5337,6 +5445,38 @@ is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=1 &
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Rd_GPR64 = tmp_1;
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}
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# C6.2.285 SMSTART page C6-1802 line 106497 MATCH xd503417f/mask=xfffff9ff
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# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
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# CONSTRUCT xd503417f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES
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# xd503417f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR
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# b_0031=110101010000001101000..101111111
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SVAmodeOp: "SM" is b_0911=0x1 {}
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SVAmodeOp: "ZA" is b_0911=0x2 {}
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SVAmodeOp: "" is b_0911=0x3 {}
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define pcodeop sveStreamingModeStart;
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define pcodeop sveStreamingModeStop;
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:smstart "{"^SVAmodeOp^"}"
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is b_1131=0x1aa068 & SVAmodeOp & b_08=1 & b_0507=0x3 & op4=0xf {
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sveStreamingModeStart(SVAmodeOp);
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}
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# C6.2.286 SMSTOP page C6-1804 line 106604 MATCH xd503407f/mask=xfffff9ff
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# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
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# CONSTRUCT xd503407f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES
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# xd503407f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR
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# b_0031=110101010000001101000..001111111
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:smstop "{"^SVAmodeOp^"}"
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is b_1131=0x1aa068 & SVAmodeOp & b_08=0 & b_0507=0x3 & op4=0xf {
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sveStreamingModeStop(SVAmodeOp);
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}
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# C6.2.288 SMULH page C6-1808 line 106800 MATCH x9b400000/mask=xffe08000
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# CONSTRUCT x9b400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
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# AUNIT --inst x9b400000/mask=xffe08000 --status pass
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@ -7165,6 +7305,17 @@ is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=2 & Rt=0x1f
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WaitForEvent();
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}
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# C6.2.397 WFET page C6-2005 line 117387 MATCH xd5031000/mask=xffffffe0
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# CONSTRUCT xd5031000/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
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# xd5031000/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR
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# b_0031=110101010000001100010000000.....
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:wfet Rd_GPR64
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is b_0531=0x6a81880 & Rd_GPR64
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{
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WaitForEvent(Rd_GPR64);
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}
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# C6.2.398 WFI page C6-2006 line 117439 MATCH xd503207f/mask=xffffffff
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# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
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# CONSTRUCT xd503207f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
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@ -7176,6 +7327,17 @@ is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=3 & Rt=0x1f
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WaitForInterrupt();
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}
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# C6.2.399 WFIT page C6-2007 line 117477 MATCH xd5031020/mask=xffffffe0
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# CONSTRUCT xd5031020/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
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# xd5031020/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR
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# b_0031=110101010000001100010000001.....
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:wfit Rd_GPR64
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is b_0531=0x6a81881 & Rd_GPR64
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{
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WaitForInterrupt(Rd_GPR64);
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}
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# C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xdac143e0/mask=xfffffbe0
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# CONSTRUCT xdac147e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
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# AUNIT --inst xdac147e0/mask=xffffffe0 --status noqemu
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@ -7652,6 +7814,48 @@ is b_1031=0b1101100111100000000000 & Rt_GPR64 & Rn_GPR64xsp
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}
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# C6.2.132 LD64B page C6-1488 line 88475 MATCH xf83fd000/mask=xfffffc00
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# CONSTRUCT xf83fd000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
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# xf83fd000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR
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# b_0031=1111100000111111110100..........
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# Single-copy Atomic 64-byte Load
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:ld64b Rn_GPR64, [Rt_GPR64xsp]
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is b_1031=0x3e0ff4 & Rn_GPR64 & Rt_GPR64xsp {
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Rn_GPR64 = *Rt_GPR64xsp;
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}
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# C6.2.292 ST64B page C6-1813 line 107121 MATCH xf83f9000/mask=xfffffc00
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# CONSTRUCT xf83f9000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
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:st64b Rn_GPR64, [Rt_GPR64xsp]
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is b_1031=0x3e0fe4 & Rn_GPR64 & Rt_GPR64xsp {
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*Rt_GPR64xsp = Rn_GPR64;
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}
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# C6.2.293 ST64BV page C6-1814 line 107190 MATCH xf820b000/mask=xffe0fc00
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# CONSTRUCT xf820b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
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define pcodeop store64ByteAtomic;
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:st64bv Rs_GPR64, Rn_GPR64, [Rt_GPR64xsp]
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is b_2131=0x7c1 & Rs_GPR64 & b_1015=0x2c & Rn_GPR64 & Rt_GPR64xsp {
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*Rt_GPR64xsp = Rn_GPR64;
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Rs_GPR64 = store64ByteAtomic(Rn_GPR64, Rt_GPR64xsp);
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}
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# C6.2.294 ST64BV0 page C6-1816 line 107284 MATCH xf820a000/mask=xffe0fc00
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# CONSTRUCT xf820a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
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:st64bv0
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is b_2131=0b11111000001 & Rs_GPR64 & b_1015=0x28 & Rn_GPR64 & Rt_GPR64xsp {
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local st64bv_addr:8 = (Rt_GPR64xsp & 0xffff0000) | (accdata & 0xffff);
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*st64bv_addr = Rn_GPR64;
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Rs_GPR64 = store64ByteAtomic(Rn_GPR64, st64bv_addr);
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}
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addrGranuleIndexed_checkAlignment: addrGranuleIndexed is Rn=0b11111 & addrGranuleIndexed { export addrGranuleIndexed; } # don't check alignment if we're working with the stack, it's assumed to be 16-byte-aligned, though that is technically optional
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addrGranuleIndexed_checkAlignment: addrGranuleIndexed is Rn & addrGranuleIndexed { tmp:8 = addrGranuleIndexed; RequireGranuleAlignment(tmp); export tmp; } # if the address in tmp is derived from sp, the error condition in RequireGranuleAlignment can still be an unreachable block; it doesn't seem possible to avoid the decompiler message in that case
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@ -8103,6 +8307,48 @@ is sf=1 & b_30=0 & S & SBIT_CZNO & b_2128=0b11010110 & b_1015=0b000000 & Rd_GPR6
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}
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# C6.2.376 TCANCEL page C6-1974 line 115824 MATCH xd4600000/mask=xffe0001f
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# CONSTRUCT xd4600000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
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define pcodeop cancelTransaction;
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:tcancel "#"^imm16
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is b_2131=0x6a3 & imm16 & b_0519 & b_2020 & b_0004=0x0 {
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local tmp:2 = imm16;
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local reason:2 = b_0519;
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local retry:1 = b_2020;
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cancelTransaction(reason, retry);
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}
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# C6.2.377 TCOMMIT page C6-1975 line 115871 MATCH xd503307f/mask=xffffffff
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# CONSTRUCT xd503307f/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES
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define pcodeop commitTransaction;
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:tcommit
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is b_0031=0xd503307f {
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commitTransaction();
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}
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# C6.2.379 TSTART page C6-1979 line 116075
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define pcodeop transactionStart;
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:tstart Rd_GPR64
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is b_0531=0x6a9193a & Rd_GPR64 {
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transactionStart(Rd_GPR64);
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}
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|
||||
# C6.2.380 TTEST page C6-1981 line 116175
|
||||
|
||||
define pcodeop transactionDepth;
|
||||
:ttest Rd_GPR64
|
||||
is b_0531=0x6a9198b & Rd_GPR64 {
|
||||
Rd_GPR64 = transactionDepth();
|
||||
}
|
||||
|
||||
|
||||
|
||||
# C6.2.387 UDF page C6-1993 line 116744 MATCH x00000000/mask=xffff0000
|
||||
# CONSTRUCT x00000000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
|
||||
# Undefined instruction
|
||||
|
|
@ -8135,567 +8381,3 @@ is b_1231=0b11010101000000000100 & b_0007=0b00111111
|
|||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
################################ Need implementation
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
# C6.2.27 BC.cond page C6-1192 line 70348 MATCH x54000010/mask=xff000010
|
||||
# CONSTRUCT x54000010/mask=xff000010 MATCHED 1 DOCUMENTED OPCODES
|
||||
# x54000010/mask=xff000010 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=01010100...................1....
|
||||
|
||||
:bc
|
||||
is b_2431=0b01010100 & imm19 & b_0404=0b1 & cond
|
||||
unimpl
|
||||
|
||||
# C6.2.68 CPYFP, CPYFM, CPYFE page C6-1262 line 73913 MATCH x19000400/mask=x3f20fc00
|
||||
# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00
|
||||
# CONSTRUCT x19000400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x19000400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....000001..........
|
||||
|
||||
:cpyfp
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b000001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.69 CPYFPN, CPYFMN, CPYFEN page C6-1267 line 74246 MATCH x1900c400/mask=x3f20fc00
|
||||
# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00
|
||||
# CONSTRUCT x1900c400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1900c400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....110001..........
|
||||
|
||||
:cpyfpn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b110001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.70 CPYFPRN, CPYFMRN, CPYFERN page C6-1272 line 74579 MATCH x19008400/mask=x3f20fc00
|
||||
# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00
|
||||
# CONSTRUCT x19008400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x19008400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....100001..........
|
||||
|
||||
:cpyfprn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b100001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.71 CPYFPRT, CPYFMRT, CPYFERT page C6-1277 line 74912 MATCH x19002400/mask=x3f20fc00
|
||||
# C6.2.277 SETPN, SETMN, SETEN page C6-1784 line 105360 MATCH x19c02400/mask=x3fe03c00
|
||||
# CONSTRUCT x19002400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x19002400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....001001..........
|
||||
|
||||
:cpyfprt
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b001001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.72 CPYFPRTN, CPYFMRTN, CPYFERTN page C6-1282 line 75245 MATCH x1900e400/mask=x3f20fc00
|
||||
# C6.2.277 SETPN, SETMN, SETEN page C6-1784 line 105360 MATCH x19c02400/mask=x3fe03c00
|
||||
# CONSTRUCT x1900e400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1900e400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....111001..........
|
||||
|
||||
:cpyfprtn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b111001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.73 CPYFPRTRN, CPYFMRTRN, CPYFERTRN page C6-1287 line 75578 MATCH x1900a400/mask=x3f20fc00
|
||||
# C6.2.277 SETPN, SETMN, SETEN page C6-1784 line 105360 MATCH x19c02400/mask=x3fe03c00
|
||||
# CONSTRUCT x1900a400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1900a400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....101001..........
|
||||
|
||||
:cpyfprtrn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b101001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.74 CPYFPRTWN, CPYFMRTWN, CPYFERTWN page C6-1292 line 75911 MATCH x19006400/mask=x3f20fc00
|
||||
# C6.2.277 SETPN, SETMN, SETEN page C6-1784 line 105360 MATCH x19c02400/mask=x3fe03c00
|
||||
# CONSTRUCT x19006400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x19006400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....011001..........
|
||||
|
||||
:cpyfprtwn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b011001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.75 CPYFPT, CPYFMT, CPYFET page C6-1297 line 76244 MATCH x19003400/mask=x3f20fc00
|
||||
# C6.2.279 SETPTN, SETMTN, SETETN page C6-1792 line 105936 MATCH x19c03400/mask=x3fe03c00
|
||||
# CONSTRUCT x19003400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x19003400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....001101..........
|
||||
|
||||
:cpyfpt
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b001101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.76 CPYFPTN, CPYFMTN, CPYFETN page C6-1302 line 76577 MATCH x1900f400/mask=x3f20fc00
|
||||
# C6.2.279 SETPTN, SETMTN, SETETN page C6-1792 line 105936 MATCH x19c03400/mask=x3fe03c00
|
||||
# CONSTRUCT x1900f400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1900f400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....111101..........
|
||||
|
||||
:cpyfptn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b111101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.77 CPYFPTRN, CPYFMTRN, CPYFETRN page C6-1307 line 76910 MATCH x1900b400/mask=x3f20fc00
|
||||
# C6.2.279 SETPTN, SETMTN, SETETN page C6-1792 line 105936 MATCH x19c03400/mask=x3fe03c00
|
||||
# CONSTRUCT x1900b400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1900b400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....101101..........
|
||||
|
||||
:cpyfptrn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b101101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.78 CPYFPTWN, CPYFMTWN, CPYFETWN page C6-1312 line 77243 MATCH x19007400/mask=x3f20fc00
|
||||
# C6.2.279 SETPTN, SETMTN, SETETN page C6-1792 line 105936 MATCH x19c03400/mask=x3fe03c00
|
||||
# CONSTRUCT x19007400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x19007400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....011101..........
|
||||
|
||||
:cpyfptwn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b011101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.79 CPYFPWN, CPYFMWN, CPYFEWN page C6-1317 line 77576 MATCH x19004400/mask=x3f20fc00
|
||||
# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00
|
||||
# CONSTRUCT x19004400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x19004400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....010001..........
|
||||
|
||||
:cpyfpwn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b010001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.80 CPYFPWT, CPYFMWT, CPYFEWT page C6-1322 line 77909 MATCH x19001400/mask=x3f20fc00
|
||||
# C6.2.278 SETPT, SETMT, SETET page C6-1788 line 105648 MATCH x19c01400/mask=x3fe03c00
|
||||
# CONSTRUCT x19001400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x19001400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....000101..........
|
||||
|
||||
:cpyfpwt
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b000101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.81 CPYFPWTN, CPYFMWTN, CPYFEWTN page C6-1327 line 78242 MATCH x1900d400/mask=x3f20fc00
|
||||
# C6.2.278 SETPT, SETMT, SETET page C6-1788 line 105648 MATCH x19c01400/mask=x3fe03c00
|
||||
# CONSTRUCT x1900d400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1900d400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....110101..........
|
||||
|
||||
:cpyfpwtn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b110101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.82 CPYFPWTRN, CPYFMWTRN, CPYFEWTRN page C6-1332 line 78575 MATCH x19009400/mask=x3f20fc00
|
||||
# C6.2.278 SETPT, SETMT, SETET page C6-1788 line 105648 MATCH x19c01400/mask=x3fe03c00
|
||||
# CONSTRUCT x19009400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x19009400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....100101..........
|
||||
|
||||
:cpyfpwtrn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b100101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.83 CPYFPWTWN, CPYFMWTWN, CPYFEWTWN page C6-1337 line 78908 MATCH x19005400/mask=x3f20fc00
|
||||
# C6.2.278 SETPT, SETMT, SETET page C6-1788 line 105648 MATCH x19c01400/mask=x3fe03c00
|
||||
# CONSTRUCT x19005400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x19005400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001..0.....010101..........
|
||||
|
||||
:cpyfpwtwn
|
||||
is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b010101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.84 CPYP, CPYM, CPYE page C6-1342 line 79241 MATCH x1d000400/mask=x3f20fc00
|
||||
# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d000400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d000400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....000001..........
|
||||
|
||||
:cpyp
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b000001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.85 CPYPN, CPYMN, CPYEN page C6-1348 line 79655 MATCH x1d00c400/mask=x3f20fc00
|
||||
# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d00c400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d00c400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....110001..........
|
||||
|
||||
:cpypn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b110001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.86 CPYPRN, CPYMRN, CPYERN page C6-1354 line 80068 MATCH x1d008400/mask=x3f20fc00
|
||||
# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d008400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d008400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....100001..........
|
||||
|
||||
:cpyprn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b100001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.87 CPYPRT, CPYMRT, CPYERT page C6-1360 line 80481 MATCH x1d002400/mask=x3f20fc00
|
||||
# C6.2.273 SETGPN, SETGMN, SETGEN page C6-1765 line 104007 MATCH x1dc02400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d002400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d002400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....001001..........
|
||||
|
||||
:cpyprt
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b001001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.88 CPYPRTN, CPYMRTN, CPYERTN page C6-1366 line 80894 MATCH x1d00e400/mask=x3f20fc00
|
||||
# C6.2.273 SETGPN, SETGMN, SETGEN page C6-1765 line 104007 MATCH x1dc02400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d00e400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d00e400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....111001..........
|
||||
|
||||
:cpyprtn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b111001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.89 CPYPRTRN, CPYMRTRN, CPYERTRN page C6-1372 line 81307 MATCH x1d00a400/mask=x3f20fc00
|
||||
# C6.2.273 SETGPN, SETGMN, SETGEN page C6-1765 line 104007 MATCH x1dc02400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d00a400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d00a400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....101001..........
|
||||
|
||||
:cpyprtrn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b101001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.90 CPYPRTWN, CPYMRTWN, CPYERTWN page C6-1378 line 81720 MATCH x1d006400/mask=x3f20fc00
|
||||
# C6.2.273 SETGPN, SETGMN, SETGEN page C6-1765 line 104007 MATCH x1dc02400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d006400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d006400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....011001..........
|
||||
|
||||
:cpyprtwn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b011001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.91 CPYPT, CPYMT, CPYET page C6-1384 line 82133 MATCH x1d003400/mask=x3f20fc00
|
||||
# C6.2.275 SETGPTN, SETGMTN, SETGETN page C6-1775 line 104717 MATCH x1dc03400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d003400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d003400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....001101..........
|
||||
|
||||
:cpypt
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b001101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.92 CPYPTN, CPYMTN, CPYETN page C6-1390 line 82546 MATCH x1d00f400/mask=x3f20fc00
|
||||
# C6.2.275 SETGPTN, SETGMTN, SETGETN page C6-1775 line 104717 MATCH x1dc03400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d00f400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d00f400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....111101..........
|
||||
|
||||
:cpyptn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b111101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.93 CPYPTRN, CPYMTRN, CPYETRN page C6-1396 line 82959 MATCH x1d00b400/mask=x3f20fc00
|
||||
# C6.2.275 SETGPTN, SETGMTN, SETGETN page C6-1775 line 104717 MATCH x1dc03400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d00b400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d00b400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....101101..........
|
||||
|
||||
:cpyptrn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b101101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.94 CPYPTWN, CPYMTWN, CPYETWN page C6-1402 line 83372 MATCH x1d007400/mask=x3f20fc00
|
||||
# C6.2.275 SETGPTN, SETGMTN, SETGETN page C6-1775 line 104717 MATCH x1dc03400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d007400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d007400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....011101..........
|
||||
|
||||
:cpyptwn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b011101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.95 CPYPWN, CPYMWN, CPYEWN page C6-1408 line 83785 MATCH x1d004400/mask=x3f20fc00
|
||||
# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d004400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d004400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....010001..........
|
||||
|
||||
:cpypwn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b010001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.96 CPYPWT, CPYMWT, CPYEWT page C6-1414 line 84198 MATCH x1d001400/mask=x3f20fc00
|
||||
# C6.2.274 SETGPT, SETGMT, SETGET page C6-1770 line 104362 MATCH x1dc01400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d001400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d001400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....000101..........
|
||||
|
||||
:cpypwt
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b000101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.97 CPYPWTN, CPYMWTN, CPYEWTN page C6-1420 line 84611 MATCH x1d00d400/mask=x3f20fc00
|
||||
# C6.2.274 SETGPT, SETGMT, SETGET page C6-1770 line 104362 MATCH x1dc01400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d00d400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d00d400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....110101..........
|
||||
|
||||
:cpypwtn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b110101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.98 CPYPWTRN, CPYMWTRN, CPYEWTRN page C6-1426 line 85024 MATCH x1d009400/mask=x3f20fc00
|
||||
# C6.2.274 SETGPT, SETGMT, SETGET page C6-1770 line 104362 MATCH x1dc01400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d009400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d009400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....100101..........
|
||||
|
||||
:cpypwtrn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b100101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.99 CPYPWTWN, CPYMWTWN, CPYEWTWN page C6-1432 line 85437 MATCH x1d005400/mask=x3f20fc00
|
||||
# C6.2.274 SETGPT, SETGMT, SETGET page C6-1770 line 104362 MATCH x1dc01400/mask=x3fe03c00
|
||||
# CONSTRUCT x1d005400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
|
||||
# x1d005400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101..0.....010101..........
|
||||
|
||||
:cpypwtwn
|
||||
is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b010101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503323f/mask=xfffff3ff
|
||||
# CONSTRUCT xd503323f/mask=xfffff3ff MATCHED 1 DOCUMENTED OPCODES
|
||||
# xd503323f/mask=xfffff3ff NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=11010101000000110011..1000111111
|
||||
|
||||
:dsb
|
||||
is b_1231=0b11010101000000110011 & imm2 & b_0009=0b1000111111
|
||||
unimpl
|
||||
|
||||
# C6.2.132 LD64B page C6-1488 line 88475 MATCH xf83fd000/mask=xfffffc00
|
||||
# CONSTRUCT xf83fd000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
|
||||
# xf83fd000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=1111100000111111110100..........
|
||||
|
||||
:ld64b
|
||||
is b_1031=0b1111100000111111110100 & Rn & Rt
|
||||
unimpl
|
||||
|
||||
# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00
|
||||
# C6.2.84 CPYP, CPYM, CPYE page C6-1342 line 79241 MATCH x1d000400/mask=x3f20fc00
|
||||
# C6.2.85 CPYPN, CPYMN, CPYEN page C6-1348 line 79655 MATCH x1d00c400/mask=x3f20fc00
|
||||
# C6.2.86 CPYPRN, CPYMRN, CPYERN page C6-1354 line 80068 MATCH x1d008400/mask=x3f20fc00
|
||||
# C6.2.95 CPYPWN, CPYMWN, CPYEWN page C6-1408 line 83785 MATCH x1d004400/mask=x3f20fc00
|
||||
# CONSTRUCT x1dc00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
|
||||
# x1dc00400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101110.......0001..........
|
||||
|
||||
:setgp
|
||||
is size & b_2129=0b011101110 & Rs & x & x & b_1013=0b0001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.273 SETGPN, SETGMN, SETGEN page C6-1765 line 104007 MATCH x1dc02400/mask=x3fe03c00
|
||||
# C6.2.87 CPYPRT, CPYMRT, CPYERT page C6-1360 line 80481 MATCH x1d002400/mask=x3f20fc00
|
||||
# C6.2.88 CPYPRTN, CPYMRTN, CPYERTN page C6-1366 line 80894 MATCH x1d00e400/mask=x3f20fc00
|
||||
# C6.2.89 CPYPRTRN, CPYMRTRN, CPYERTRN page C6-1372 line 81307 MATCH x1d00a400/mask=x3f20fc00
|
||||
# C6.2.90 CPYPRTWN, CPYMRTWN, CPYERTWN page C6-1378 line 81720 MATCH x1d006400/mask=x3f20fc00
|
||||
# CONSTRUCT x1dc02400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
|
||||
# x1dc02400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101110.......1001..........
|
||||
|
||||
:setgpn
|
||||
is size & b_2129=0b011101110 & Rs & x & x & b_1013=0b1001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.274 SETGPT, SETGMT, SETGET page C6-1770 line 104362 MATCH x1dc01400/mask=x3fe03c00
|
||||
# C6.2.96 CPYPWT, CPYMWT, CPYEWT page C6-1414 line 84198 MATCH x1d001400/mask=x3f20fc00
|
||||
# C6.2.97 CPYPWTN, CPYMWTN, CPYEWTN page C6-1420 line 84611 MATCH x1d00d400/mask=x3f20fc00
|
||||
# C6.2.98 CPYPWTRN, CPYMWTRN, CPYEWTRN page C6-1426 line 85024 MATCH x1d009400/mask=x3f20fc00
|
||||
# C6.2.99 CPYPWTWN, CPYMWTWN, CPYEWTWN page C6-1432 line 85437 MATCH x1d005400/mask=x3f20fc00
|
||||
# CONSTRUCT x1dc01400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
|
||||
# x1dc01400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101110.......0101..........
|
||||
|
||||
:setgpt
|
||||
is size & b_2129=0b011101110 & Rs & x & x & b_1013=0b0101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.275 SETGPTN, SETGMTN, SETGETN page C6-1775 line 104717 MATCH x1dc03400/mask=x3fe03c00
|
||||
# C6.2.91 CPYPT, CPYMT, CPYET page C6-1384 line 82133 MATCH x1d003400/mask=x3f20fc00
|
||||
# C6.2.92 CPYPTN, CPYMTN, CPYETN page C6-1390 line 82546 MATCH x1d00f400/mask=x3f20fc00
|
||||
# C6.2.93 CPYPTRN, CPYMTRN, CPYETRN page C6-1396 line 82959 MATCH x1d00b400/mask=x3f20fc00
|
||||
# C6.2.94 CPYPTWN, CPYMTWN, CPYETWN page C6-1402 line 83372 MATCH x1d007400/mask=x3f20fc00
|
||||
# CONSTRUCT x1dc03400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
|
||||
# x1dc03400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011101110.......1101..........
|
||||
|
||||
:setgptn
|
||||
is size & b_2129=0b011101110 & Rs & x & x & b_1013=0b1101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00
|
||||
# C6.2.68 CPYFP, CPYFM, CPYFE page C6-1262 line 73913 MATCH x19000400/mask=x3f20fc00
|
||||
# C6.2.69 CPYFPN, CPYFMN, CPYFEN page C6-1267 line 74246 MATCH x1900c400/mask=x3f20fc00
|
||||
# C6.2.70 CPYFPRN, CPYFMRN, CPYFERN page C6-1272 line 74579 MATCH x19008400/mask=x3f20fc00
|
||||
# C6.2.79 CPYFPWN, CPYFMWN, CPYFEWN page C6-1317 line 77576 MATCH x19004400/mask=x3f20fc00
|
||||
# CONSTRUCT x19c00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
|
||||
# x19c00400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001110.......0001..........
|
||||
|
||||
:setp
|
||||
is size & b_2129=0b011001110 & Rs & x & x & b_1013=0b0001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.277 SETPN, SETMN, SETEN page C6-1784 line 105360 MATCH x19c02400/mask=x3fe03c00
|
||||
# C6.2.71 CPYFPRT, CPYFMRT, CPYFERT page C6-1277 line 74912 MATCH x19002400/mask=x3f20fc00
|
||||
# C6.2.72 CPYFPRTN, CPYFMRTN, CPYFERTN page C6-1282 line 75245 MATCH x1900e400/mask=x3f20fc00
|
||||
# C6.2.73 CPYFPRTRN, CPYFMRTRN, CPYFERTRN page C6-1287 line 75578 MATCH x1900a400/mask=x3f20fc00
|
||||
# C6.2.74 CPYFPRTWN, CPYFMRTWN, CPYFERTWN page C6-1292 line 75911 MATCH x19006400/mask=x3f20fc00
|
||||
# CONSTRUCT x19c02400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
|
||||
# x19c02400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001110.......1001..........
|
||||
|
||||
:setpn
|
||||
is size & b_2129=0b011001110 & Rs & x & x & b_1013=0b1001 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.278 SETPT, SETMT, SETET page C6-1788 line 105648 MATCH x19c01400/mask=x3fe03c00
|
||||
# C6.2.80 CPYFPWT, CPYFMWT, CPYFEWT page C6-1322 line 77909 MATCH x19001400/mask=x3f20fc00
|
||||
# C6.2.81 CPYFPWTN, CPYFMWTN, CPYFEWTN page C6-1327 line 78242 MATCH x1900d400/mask=x3f20fc00
|
||||
# C6.2.82 CPYFPWTRN, CPYFMWTRN, CPYFEWTRN page C6-1332 line 78575 MATCH x19009400/mask=x3f20fc00
|
||||
# C6.2.83 CPYFPWTWN, CPYFMWTWN, CPYFEWTWN page C6-1337 line 78908 MATCH x19005400/mask=x3f20fc00
|
||||
# CONSTRUCT x19c01400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
|
||||
# x19c01400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001110.......0101..........
|
||||
|
||||
:setpt
|
||||
is size & b_2129=0b011001110 & Rs & x & x & b_1013=0b0101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.279 SETPTN, SETMTN, SETETN page C6-1792 line 105936 MATCH x19c03400/mask=x3fe03c00
|
||||
# C6.2.75 CPYFPT, CPYFMT, CPYFET page C6-1297 line 76244 MATCH x19003400/mask=x3f20fc00
|
||||
# C6.2.76 CPYFPTN, CPYFMTN, CPYFETN page C6-1302 line 76577 MATCH x1900f400/mask=x3f20fc00
|
||||
# C6.2.77 CPYFPTRN, CPYFMTRN, CPYFETRN page C6-1307 line 76910 MATCH x1900b400/mask=x3f20fc00
|
||||
# C6.2.78 CPYFPTWN, CPYFMTWN, CPYFETWN page C6-1312 line 77243 MATCH x19007400/mask=x3f20fc00
|
||||
# CONSTRUCT x19c03400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
|
||||
# x19c03400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=..011001110.......1101..........
|
||||
|
||||
:setptn
|
||||
is size & b_2129=0b011001110 & Rs & x & x & b_1013=0b1101 & Rn & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.285 SMSTART page C6-1802 line 106497 MATCH xd503417f/mask=xfffff9ff
|
||||
# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
|
||||
# CONSTRUCT xd503417f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES
|
||||
# xd503417f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=110101010000001101000..101111111
|
||||
|
||||
:smstart
|
||||
is b_1131=0b110101010000001101000 & x & x & b_0008=0b101111111
|
||||
unimpl
|
||||
|
||||
# C6.2.286 SMSTOP page C6-1804 line 106604 MATCH xd503407f/mask=xfffff9ff
|
||||
# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
|
||||
# CONSTRUCT xd503407f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES
|
||||
# xd503407f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=110101010000001101000..001111111
|
||||
|
||||
:smstop
|
||||
is b_1131=0b110101010000001101000 & x & x & b_0008=0b001111111
|
||||
unimpl
|
||||
|
||||
# C6.2.292 ST64B page C6-1813 line 107121 MATCH xf83f9000/mask=xfffffc00
|
||||
# CONSTRUCT xf83f9000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
|
||||
# xf83f9000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=1111100000111111100100..........
|
||||
|
||||
:st64b
|
||||
is b_1031=0b1111100000111111100100 & Rn & Rt
|
||||
unimpl
|
||||
|
||||
# C6.2.293 ST64BV page C6-1814 line 107190 MATCH xf820b000/mask=xffe0fc00
|
||||
# CONSTRUCT xf820b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
|
||||
# xf820b000/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=11111000001.....101100..........
|
||||
|
||||
:st64bv
|
||||
is b_2131=0b11111000001 & Rs & b_1015=0b101100 & Rn & Rt
|
||||
unimpl
|
||||
|
||||
# C6.2.294 ST64BV0 page C6-1816 line 107284 MATCH xf820a000/mask=xffe0fc00
|
||||
# CONSTRUCT xf820a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
|
||||
# xf820a000/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=11111000001.....101000..........
|
||||
|
||||
:st64bv0
|
||||
is b_2131=0b11111000001 & Rs & b_1015=0b101000 & Rn & Rt
|
||||
unimpl
|
||||
|
||||
# C6.2.376 TCANCEL page C6-1974 line 115824 MATCH xd4600000/mask=xffe0001f
|
||||
# CONSTRUCT xd4600000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
|
||||
# xd4600000/mask=xffe0001f NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=11010100011................00000
|
||||
|
||||
:tcancel
|
||||
is b_2131=0b11010100011 & imm16 & b_0004=0b00000
|
||||
unimpl
|
||||
|
||||
# C6.2.377 TCOMMIT page C6-1975 line 115871 MATCH xd503307f/mask=xffffffff
|
||||
# CONSTRUCT xd503307f/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES
|
||||
# xd503307f/mask=xffffffff NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=11010101000000110011000001111111
|
||||
|
||||
:tcommit
|
||||
is b_0031=0b11010101000000110011000001111111
|
||||
unimpl
|
||||
|
||||
# C6.2.397 WFET page C6-2005 line 117387 MATCH xd5031000/mask=xffffffe0
|
||||
# CONSTRUCT xd5031000/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
|
||||
# xd5031000/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=110101010000001100010000000.....
|
||||
|
||||
:wfet
|
||||
is b_0531=0b110101010000001100010000000 & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.399 WFIT page C6-2007 line 117477 MATCH xd5031020/mask=xffffffe0
|
||||
# CONSTRUCT xd5031020/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
|
||||
# xd5031020/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=110101010000001100010000001.....
|
||||
|
||||
:wfit
|
||||
is b_0531=0b110101010000001100010000001 & Rd
|
||||
unimpl
|
||||
|
||||
# C6.2.228 MRS page C6-1683 line 99588
|
||||
# xd5300000/mask=xfff00000 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=110101010011....................
|
||||
|
||||
# C6.2.379 TSTART page C6-1979 line 116075
|
||||
# xd5233060/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=110101010010001100110000011.....
|
||||
|
||||
:tstart
|
||||
is b_0531=0b110101010010001100110000011 & Rt
|
||||
unimpl
|
||||
|
||||
# C6.2.380 TTEST page C6-1981 line 116175
|
||||
# xd5233160/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR
|
||||
# b_0031=110101010010001100110001011.....
|
||||
|
||||
:ttest
|
||||
is b_0531=0b110101010010001100110001011 & Rt
|
||||
unimpl
|
||||
|
|
|
|||
|
|
@ -103,6 +103,7 @@ define register offset=0x1000 size=8
|
|||
uao
|
||||
pan
|
||||
tco
|
||||
accdata
|
||||
];
|
||||
|
||||
# System Registers
|
||||
|
|
@ -1201,6 +1202,8 @@ define token instrAARCH64 (32) endian = little
|
|||
b_0509 = (5,9)
|
||||
b_0510 = (5,10)
|
||||
b_0515 = (5,15)
|
||||
b_0519 = (5,19)
|
||||
b_0531 = (5,31)
|
||||
b_0607 = (6,7)
|
||||
b_0609 = (6,9)
|
||||
b_0610 = (6,10)
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="v8"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM8_le.sla"
|
||||
processorspec="ARMt.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="v8T"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM8_le.sla"
|
||||
processorspec="ARMtTHUMB.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -49,7 +49,7 @@
|
|||
instructionEndian="little"
|
||||
size="32"
|
||||
variant="v8LEInstruction"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM8_le.sla"
|
||||
processorspec="ARMt.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -64,7 +64,7 @@
|
|||
endian="big"
|
||||
size="32"
|
||||
variant="v8"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM8_be.sla"
|
||||
processorspec="ARMt.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -87,7 +87,7 @@
|
|||
endian="big"
|
||||
size="32"
|
||||
variant="v8T"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM8_be.sla"
|
||||
processorspec="ARMtTHUMB.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -104,7 +104,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="v7"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM7_le.sla"
|
||||
processorspec="ARMt.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -124,7 +124,7 @@
|
|||
instructionEndian="little"
|
||||
size="32"
|
||||
variant="v7LEInstruction"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM7_le.sla"
|
||||
processorspec="ARMt.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -139,7 +139,7 @@
|
|||
endian="big"
|
||||
size="32"
|
||||
variant="v7"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM7_be.sla"
|
||||
processorspec="ARMt.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -157,7 +157,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="Cortex"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM7_le.sla"
|
||||
processorspec="ARMCortex.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -177,7 +177,7 @@
|
|||
endian="big"
|
||||
size="32"
|
||||
variant="Cortex"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM7_be.sla"
|
||||
processorspec="ARMCortex.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -196,7 +196,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="v6"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM6_le.sla"
|
||||
processorspec="ARMt_v6.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -216,7 +216,7 @@
|
|||
endian="big"
|
||||
size="32"
|
||||
variant="v6"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM6_be.sla"
|
||||
processorspec="ARMt_v6.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -236,7 +236,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="v5t"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM5t_le.sla"
|
||||
processorspec="ARMt_v45.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -254,7 +254,7 @@
|
|||
endian="big"
|
||||
size="32"
|
||||
variant="v5t"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM5t_be.sla"
|
||||
processorspec="ARMt_v45.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -272,7 +272,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="v5"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM5_le.sla"
|
||||
processorspec="ARM_v45.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -304,7 +304,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="v4t"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM4t_le.sla"
|
||||
processorspec="ARMt_v45.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -321,7 +321,7 @@
|
|||
endian="big"
|
||||
size="32"
|
||||
variant="v4t"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM4t_be.sla"
|
||||
processorspec="ARMt_v45.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -338,7 +338,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="v4"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM4_le.sla"
|
||||
processorspec="ARM_v45.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
@ -358,7 +358,7 @@
|
|||
endian="big"
|
||||
size="32"
|
||||
variant="v4"
|
||||
version="1.103"
|
||||
version="1.104"
|
||||
slafile="ARM4_be.sla"
|
||||
processorspec="ARM_v45.pspec"
|
||||
manualindexfile="../manuals/ARM.idx"
|
||||
|
|
|
|||
|
|
@ -103,6 +103,22 @@ define token instrArm (32)
|
|||
Qm1=(0,3)
|
||||
Dn0=(16,19)
|
||||
Dd0=(12,15)
|
||||
Dd_1=(12,15)
|
||||
Dd_2=(12,15)
|
||||
Dd_3=(12,15)
|
||||
Dd_4=(12,15)
|
||||
Dd_5=(12,15)
|
||||
Dd_6=(12,15)
|
||||
Dd_7=(12,15)
|
||||
Dd_8=(12,15)
|
||||
Dd_9=(12,15)
|
||||
Dd_10=(12,15)
|
||||
Dd_11=(12,15)
|
||||
Dd_12=(12,15)
|
||||
Dd_13=(12,15)
|
||||
Dd_14=(12,15)
|
||||
Dd_15=(12,15)
|
||||
Dd_16=(12,15)
|
||||
Dm0=(0,3)
|
||||
Dn1=(16,19)
|
||||
Dd1=(12,15)
|
||||
|
|
@ -117,6 +133,8 @@ define token instrArm (32)
|
|||
Sd1=(12,15)
|
||||
Sm1=(0,3)
|
||||
Sm1next=(0,3)
|
||||
Sm0_3=(0,2)
|
||||
Sm1_3=(0,2)
|
||||
cmode=(8,11)
|
||||
|
||||
|
||||
|
|
@ -286,12 +304,14 @@ define token instrArm (32)
|
|||
thv_Sm1=(16,19)
|
||||
thv_Sm1next=(16,19)
|
||||
thv_cmode=(24,27)
|
||||
thv_Sm0_3=(16,18)
|
||||
thv_Sm1_3=(16,18)
|
||||
|
||||
thv_Rd=(28,31)
|
||||
thv_Rt=(28,31)
|
||||
thv_Rn=(0,3)
|
||||
thv_Rm=(16,19)
|
||||
thv_Rt2=(24,27)
|
||||
thv_Rt2=(24,27)
|
||||
thv_immed=(16,23)
|
||||
|
||||
# Arbitrary bit fields for 32-bit Little Endian Thumb
|
||||
|
|
@ -447,6 +467,8 @@ define token instrArm (32)
|
|||
thv_Sd1=(12,15)
|
||||
thv_Sm1=(0,3)
|
||||
thv_Sm1next=(0,3)
|
||||
thv_Sm0_3=(0,2)
|
||||
thv_Sm1_3=(0,2)
|
||||
thv_cmode=(8,11)
|
||||
|
||||
thv_Rd=(12,15)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -14,19 +14,19 @@ crc32_type: "w" is TMode=1 & thv_c0405=0b10 { }
|
|||
|
||||
define pcodeop Crc32Calc;
|
||||
|
||||
# F5.1.39,40 p2650,2653 CRC32,CRC32C A1
|
||||
# F5.1.39,40 p7226,7229 CRC32,CRC32C A1
|
||||
:crc32^crc32_type Rd,Rn,Rm
|
||||
is TMode=0 & c2831=0b1110 & c2327=0b00010 & c2020=0 & c0407=0b0100 & c1011=0b00 & c0808=0
|
||||
& crc32_type & Rn & Rd & Rm
|
||||
{ Rd = Crc32Calc(Rn,Rm); }
|
||||
|
||||
# F5.1.39 p2650 CRC32 T1
|
||||
# F5.1.39 p7226 CRC32 T1
|
||||
:crc32^crc32_type thv_Rt2,thv_Rn,thv_Rm
|
||||
is TMode=1 & thv_c2031=0b111110101100 & thv_c1215=0b1111 & thv_c0607=0b10
|
||||
& crc32_type & thv_Rn & thv_Rt2 & thv_Rm
|
||||
{ thv_Rt2 = Crc32Calc(thv_Rn,thv_Rm); }
|
||||
|
||||
# F5.1.40 p2653 CRC32C T1
|
||||
# F5.1.40 p7229 CRC32C T1
|
||||
:crc32c^crc32_type thv_Rt2,thv_Rn,thv_Rm
|
||||
is TMode=1 & thv_c2031=0b111110101101 & thv_c1215=0b1111 & thv_c0607=0b10
|
||||
& crc32_type & thv_Rn & thv_Rt2 & thv_Rm
|
||||
|
|
@ -38,12 +38,12 @@ dcps_lev:1 is TMode=1 & thv_c0001=0b01 { export 1:1; }
|
|||
dcps_lev:2 is TMode=1 & thv_c0001=0b10 { export 2:1; }
|
||||
dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
||||
|
||||
# F5.1.42 p2657 DCPS1,DCPS2,DCPS3 DSPS1 variant
|
||||
# F5.1.43 p7235 DCPS1,DCPS2,DCPS3 DSPS1 variant
|
||||
:dcps^dcps_lev
|
||||
is TMode=1 & thv_c1631=0b1111011110001111 & thv_c0215=0b10000000000000 & (thv_c0101=1 | thv_c0000=1) & dcps_lev
|
||||
{ DCPSInstruction(dcps_lev:1); }
|
||||
|
||||
# F5.1.53 p2683 LDA
|
||||
# F5.1.57 p7268 LDA
|
||||
:lda^COND Rd,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xc9f
|
||||
{
|
||||
|
|
@ -51,7 +51,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
Rd = *Rn;
|
||||
}
|
||||
|
||||
# F5.1.53 p2683 LDA
|
||||
# F5.1.57 p7268 LDA
|
||||
:lda thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1010
|
||||
& ItCond & thv_Rn & thv_Rt
|
||||
|
|
@ -60,7 +60,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
thv_Rt = *thv_Rn;
|
||||
}
|
||||
|
||||
# F5.1.54 p2684 LDAB
|
||||
# F5.1.58 p7270 LDAB
|
||||
:ldab^COND Rd,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xc9f
|
||||
{
|
||||
|
|
@ -69,7 +69,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
Rd = zext(val);
|
||||
}
|
||||
|
||||
# F5.1.54 p2684 LDAB
|
||||
# F5.1.58 p7270 LDAB
|
||||
:ldab thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1000
|
||||
& ItCond & thv_Rt & thv_Rn
|
||||
|
|
@ -79,7 +79,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
thv_Rt = zext(val);
|
||||
}
|
||||
|
||||
# F5.1.55 p2685 LDAEX
|
||||
# F5.1.59 p7272 LDAEX
|
||||
:ldaex^COND Rd,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xe9f
|
||||
{
|
||||
|
|
@ -87,7 +87,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
Rd = *Rn;
|
||||
}
|
||||
|
||||
# F5.1.55 p2685 LDAEX
|
||||
# F5.1.59 p7272 LDAEX
|
||||
:ldaex thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1110
|
||||
& ItCond & thv_Rt & thv_Rn
|
||||
|
|
@ -96,7 +96,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
thv_Rt = *thv_Rn;
|
||||
}
|
||||
|
||||
# F5.1.56 p2687 LDAEXB
|
||||
# F5.1.60 p7274 LDAEXB
|
||||
:ldaexb^COND Rd,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xe9f
|
||||
{
|
||||
|
|
@ -105,7 +105,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
Rd = zext(val);
|
||||
}
|
||||
|
||||
# F5.1.56 p2687 LDAEXB
|
||||
# F5.1.60 p7274 LDAEXB
|
||||
:ldaexb thv_Rt,thv_Rn
|
||||
is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1100
|
||||
& ItCond & thv_Rt & thv_Rn
|
||||
|
|
@ -115,7 +115,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
thv_Rt = zext(val);
|
||||
}
|
||||
|
||||
# F5.1.57 p2689 LDAEXD
|
||||
# F5.1.61 p7274 LDAEXD
|
||||
:ldaexd^COND Rd,Rd2,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xe9f
|
||||
{
|
||||
|
|
@ -129,7 +129,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
@endif # ENDIAN == "little"
|
||||
}
|
||||
|
||||
# F5.1.57 p2689 LDAEXD
|
||||
# F5.1.61 p7274 LDAEXD
|
||||
:ldaexd thv_Rt,thv_Rt2,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1111
|
||||
& ItCond & thv_Rt & thv_Rt2 & thv_Rn
|
||||
|
|
@ -144,7 +144,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
@endif # ENDIAN == "little"
|
||||
}
|
||||
|
||||
# F5.1.58 p2691 LDAEXH
|
||||
# F5.1.62 p7278 LDAEXH
|
||||
:ldaexh^COND Rd,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xe9f
|
||||
{
|
||||
|
|
@ -153,7 +153,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
Rd = zext(val);
|
||||
}
|
||||
|
||||
# F5.1.58 p2691 LDAEXH
|
||||
# F5.1.62 p7278 LDAEXH
|
||||
:ldaexh thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1101
|
||||
& ItCond & thv_Rt & thv_Rn
|
||||
|
|
@ -163,7 +163,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
thv_Rt = zext(val);
|
||||
}
|
||||
|
||||
# F5.1.59 p2693 LDAH
|
||||
# F5.1.63 p7280 LDAH
|
||||
:ldah^COND Rd,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xc9f
|
||||
{
|
||||
|
|
@ -172,7 +172,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
Rd = zext(val);
|
||||
}
|
||||
|
||||
# F5.1.59 p2693 LDAH
|
||||
# F5.1.63 p7280 LDAH
|
||||
:ldah thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1001
|
||||
& ItCond & thv_Rt & thv_Rn
|
||||
|
|
@ -182,7 +182,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
thv_Rt = zext(val);
|
||||
}
|
||||
|
||||
# F5.1.178 p2969 SEVL A1 variant
|
||||
# F5.1.185 p7573 SEVL A1 variant
|
||||
:sevl^COND
|
||||
is TMode=0 & ARMcond=1 & COND & c1627=0b001100100000 & c0007=0b00000101
|
||||
{
|
||||
|
|
@ -190,7 +190,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
SendEvent();
|
||||
}
|
||||
|
||||
# F5.1.178 p2969 SEVL T2 variant
|
||||
# F5.1.185 p7573 SEVL T2 variant
|
||||
:sevl.w
|
||||
is TMode=1 & thv_c2031=0b111100111010 & thv_c1415=0b10 & thv_c1212=0 & thv_c0010=0b00000000101
|
||||
& ItCond
|
||||
|
|
@ -199,7 +199,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
SendEvent();
|
||||
}
|
||||
|
||||
# F5.1.209 p3035 STL
|
||||
# F5.1.217 p7642 STL
|
||||
:stl^COND Rm,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & c0415=0xfc9 & Rm
|
||||
{
|
||||
|
|
@ -207,7 +207,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
*Rn = Rm;
|
||||
}
|
||||
|
||||
# F5.1.209 p3035 STL
|
||||
# F5.1.217 p7642 STL
|
||||
:stl thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1010
|
||||
& ItCond & thv_Rt & thv_Rn
|
||||
|
|
@ -216,7 +216,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
*thv_Rn = thv_Rt;
|
||||
}
|
||||
|
||||
# F5.1.210 p3036 STLB
|
||||
# F5.1.218 p7644 STLB
|
||||
:stlb^COND Rm,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & c0415=0xfc9 & Rm
|
||||
{
|
||||
|
|
@ -224,7 +224,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
*:1 Rn = Rm[0,8];
|
||||
}
|
||||
|
||||
# F5.1.210 p3036 STLB
|
||||
# F5.1.218 p7644 STLB
|
||||
:stlb thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1000
|
||||
& ItCond & thv_Rt & thv_Rn
|
||||
|
|
@ -233,7 +233,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
*:1 thv_Rn = thv_Rt[0,8];
|
||||
}
|
||||
|
||||
# F5.1.211 p3037 STLEX
|
||||
# F5.1.219 p7646 STLEX
|
||||
:stlex^COND Rd,Rm,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & Rd & c0411=0xe9 & Rm
|
||||
{
|
||||
|
|
@ -242,7 +242,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
Rd = 0;
|
||||
}
|
||||
|
||||
# F5.1.211 p3037 STLEX
|
||||
# F5.1.219 p7646 STLEX
|
||||
:stlex thv_Rm,thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1110
|
||||
& ItCond & thv_Rm & thv_Rt & thv_Rn
|
||||
|
|
@ -252,7 +252,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
thv_Rm = 0;
|
||||
}
|
||||
|
||||
# F5.1.212 p3040 STLEXB
|
||||
# F5.1.220 p7649 STLEXB
|
||||
:stlexb^COND Rd,Rm,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & Rd & c0411=0xe9 & Rm
|
||||
{
|
||||
|
|
@ -261,7 +261,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
Rd = 0;
|
||||
}
|
||||
|
||||
# F5.1.212 p3040 STLEXB
|
||||
# F5.1.220 p7649 STLEXB
|
||||
:stlexb thv_Rm,thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1100
|
||||
& ItCond & thv_Rm & thv_Rt & thv_Rn
|
||||
|
|
@ -271,7 +271,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
thv_Rm = 0;
|
||||
}
|
||||
|
||||
# F5.1.213 p3042 STLEXD
|
||||
# F5.1.221 p7651 STLEXD
|
||||
:stlexd^COND Rd,Rm,Rm2,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x1a & Rn & Rd & c0411=0xe9 & Rm & Rm2
|
||||
{
|
||||
|
|
@ -286,7 +286,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
Rd = 0;
|
||||
}
|
||||
|
||||
# F5.1.213 p3042 STLEXD
|
||||
# F5.1.221 p7651 STLEXD
|
||||
:stlexd thv_Rm,thv_Rt,thv_Rt2,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1111
|
||||
& ItCond & thv_Rm & thv_Rt & thv_Rt2 & thv_Rn
|
||||
|
|
@ -302,7 +302,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
thv_Rm = 0;
|
||||
}
|
||||
|
||||
# F5.1.214 p3045 STLEXH
|
||||
# F5.1.222 p7654 STLEXH
|
||||
:stlexh^COND Rd,Rm,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & Rd & c0411=0xe9 & Rm
|
||||
{
|
||||
|
|
@ -311,7 +311,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
Rd = 0;
|
||||
}
|
||||
|
||||
# F5.1.214 p3045 STLEXH
|
||||
# F5.1.222 p7654 STLEXH
|
||||
:stlexh thv_Rm,thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1101
|
||||
& ItCond & thv_Rm & thv_Rt & thv_Rn
|
||||
|
|
@ -321,7 +321,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
thv_Rm = 0;
|
||||
}
|
||||
|
||||
# F5.1.215 p3048 STLH
|
||||
# F5.1.223 p7657 STLH
|
||||
:stlh^COND Rm,[Rn]
|
||||
is TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & c0415=0xfc9 & Rm
|
||||
{
|
||||
|
|
@ -329,7 +329,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
*:2 Rn = Rm[0,16];
|
||||
}
|
||||
|
||||
# F5.1.215 p3048 STLH
|
||||
# F5.1.223 p7657 STLH
|
||||
:stlh thv_Rt,[thv_Rn]
|
||||
is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1001
|
||||
& ItCond & thv_Rt & thv_Rn
|
||||
|
|
@ -363,11 +363,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; }
|
|||
#######
|
||||
# pcodeop declarations
|
||||
|
||||
# CryptOp(val)
|
||||
# Various crypto algorithms, too numerous for explication at
|
||||
# this time
|
||||
|
||||
define pcodeop CryptOp;
|
||||
|
||||
# FixedToFP(fp, M, N, fbits, unsigned, rounding)
|
||||
# Convert M-bit fixed point with fbits fractional bits to N-bit
|
||||
|
|
@ -416,165 +412,27 @@ define pcodeop FPRoundInt;
|
|||
|
||||
define pcodeop PolynomialMult;
|
||||
|
||||
#######
|
||||
# AESD single round decryption
|
||||
|
||||
# F6.1.1 p3235 A1/T1
|
||||
:aesd.8 Qd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001101 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001101 & thv_c0404=0))
|
||||
& Qd & Qm
|
||||
{ Qd = CryptOp(Qd | Qm); }
|
||||
|
||||
#######
|
||||
# AESE single round encryption
|
||||
|
||||
# F6.1.2 p3237 A1/T1
|
||||
:aese.8 Qd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001100 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001100 & thv_c0404=0))
|
||||
& Qd & Qm
|
||||
{ Qd = CryptOp(Qd | Qm); }
|
||||
|
||||
#######
|
||||
# AESIMC inverse mix columns
|
||||
|
||||
# F6.1.3 p3239 A1/T1
|
||||
:aesimc.8 Qd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001111 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001111 & thv_c0404=0))
|
||||
& Qd & Qm
|
||||
{ Qd = CryptOp(Qm); }
|
||||
|
||||
#######
|
||||
# AESMC mix columns
|
||||
|
||||
# F6.1.4 p3240 A1/T1
|
||||
:aesmc.8 Qd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001110 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001110 & thv_c0404=0))
|
||||
& Qd & Qm
|
||||
{ Qd = CryptOp(Qm); }
|
||||
|
||||
#######
|
||||
# SHA1C SHA1 hash update (choose)
|
||||
|
||||
# F6.1.7 p3248 A1/T1
|
||||
:sha1c.32 Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b00 & c0811=0b1100 & c0606=1 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))
|
||||
& Qn & Qd & Qm
|
||||
{ Qd = CryptOp(Qd,Qn,Qm); }
|
||||
|
||||
#######
|
||||
# SHA1H SHA1 fixed rotate
|
||||
|
||||
# F6.1.8 p3250 A1/T1
|
||||
:sha1h.32 Qd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b01 & c0611=0b001011 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b01 & thv_c0611=0b001011 & thv_c0404=0))
|
||||
& Qd & Qm
|
||||
{ Qd = CryptOp(Qm); }
|
||||
|
||||
#######
|
||||
# SHA1M SHA1 hash update (majority)
|
||||
|
||||
# F6.1.9 p3251 A1/T1
|
||||
:sha1m.32 Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b10 & c0811=0b1100 & c0606=1 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))
|
||||
& Qn & Qd & Qm
|
||||
{ Qd = CryptOp(Qd,Qn,Qm); }
|
||||
|
||||
#######
|
||||
# SHA1P SHA1 hash update (parity)
|
||||
|
||||
# F6.1.10 p3253 A1/T1
|
||||
:sha1p.32 Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b01 & c0811=0b1100 & c0606=1 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))
|
||||
& Qn & Qd & Qm
|
||||
{ Qd = CryptOp(Qd,Qn,Qm); }
|
||||
|
||||
#######
|
||||
# SHA1SU0 SHA1 schedule update 0
|
||||
|
||||
# F6.1.11 p3255 A1/T1
|
||||
:sha1su0.32 Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b11 & c0811=0b1100 & c0606=1 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))
|
||||
& Qn & Qd & Qm
|
||||
{ Qd = CryptOp(Qd,Qn,Qm); }
|
||||
|
||||
#######
|
||||
# SHA1SU1 SHA1 schedule update 1
|
||||
|
||||
# F6.1.12 p3257 A1/T1
|
||||
:sha1su1.32 Qd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c0611=0b001110 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c0611=0b001110 & thv_c0404=0))
|
||||
& Qd & Qm
|
||||
{ Qd = CryptOp(Qd,Qm); }
|
||||
|
||||
#######
|
||||
# SHA256H SHA256 hash update part 1
|
||||
|
||||
# F6.1.13 p3259 A1/T1
|
||||
:sha256h.32 Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1100 & c0606=1 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))
|
||||
& Qn & Qd & Qm
|
||||
{ Qd = CryptOp(Qd,Qn,Qm); }
|
||||
|
||||
#######
|
||||
# SHA256H2 SHA256 hash update part 2
|
||||
|
||||
# F6.1.14 p3260 A1/T1
|
||||
:sha256h2.32 Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1100 & c0606=1 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))
|
||||
& Qn & Qd & Qm
|
||||
{ Qd = CryptOp(Qd,Qn,Qm); }
|
||||
|
||||
#######
|
||||
# SHA256SU0 SHA256 schedule update 0
|
||||
|
||||
# F6.1.15 p3261 A1/T1
|
||||
:sha256su0.32 Qd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c0611=0b001111 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c0611=0b001111 & thv_c0404=0))
|
||||
& Qd & Qm
|
||||
{ Qd = CryptOp(Qd,Qm); }
|
||||
|
||||
#######
|
||||
# SHA256SU1 SHA256 schedule update 1
|
||||
|
||||
# F6.1.16 p3263 A1/T1
|
||||
:sha256su1.32 Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1100 & c0606=1 & c0404=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0))
|
||||
& Qn & Qd & Qm
|
||||
{ Qd = CryptOp(Qd,Qn,Qm); }
|
||||
|
||||
#######
|
||||
# The VCVT instructions are a large family for converting between
|
||||
# floating point numbers and integers, of all sizes and combinations
|
||||
|
||||
# F6.1.54 p3350 A1 cases size = 10 (c0809)
|
||||
# F6.1.58 p7998 A1 cases size = 10 (c0809)
|
||||
:vcvt^COND^".f64.f32" Dd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11011 & c1616=1 & c1011=0b10 & c0707=1 & c0606=1 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11011 & thv_c1616=1 & thv_c1011=0b10 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))
|
||||
& COND & Dd & Sm
|
||||
{ build COND; Dd = float2float(Sm); }
|
||||
|
||||
# F6.1.54 p3350 A1 cases size = 11 (c0809)
|
||||
# F6.1.58 p7998 A1 cases size = 11 (c0809)
|
||||
:vcvt^COND^".f32.f64" Sd,Dm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11011 & c1616=1 & c1011=0b10 & c0707=1 & c0606=1 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11011 & thv_c1616=1 & thv_c1011=0b10 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))
|
||||
& COND & Sd & Dm
|
||||
{ build COND; Sd = float2float(Dm); }
|
||||
|
||||
# F6.1.55 p3352 A1 op == 1 (c0808)
|
||||
# F6.1.59 p8000 A1 op == 1 (c0808)
|
||||
:vcvt.f32.f16 Qd,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=1))
|
||||
|
|
@ -583,7 +441,7 @@ define pcodeop PolynomialMult;
|
|||
Qd = float2float(Dm:2);
|
||||
}
|
||||
|
||||
# F6.1.55 p3352 A1 op == 0 (c0808)
|
||||
# F6.1.59 p8000 A1 op == 0 (c0808)
|
||||
:vcvt.f16.f32 Dd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=0))
|
||||
|
|
@ -632,47 +490,47 @@ vcvt_56_128_dt: ".u32.f32"
|
|||
& Qd & Qm
|
||||
{ Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_ZERO)); }
|
||||
|
||||
# F6.1.56 p3354 A1 Q == 0 (c0606)
|
||||
# F6.1.60 p8002 A1 Q == 0 (c0606)
|
||||
:vcvt^vcvt_56_64_dt Dd,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=0))
|
||||
& vcvt_56_64_dt & Dd & Dm
|
||||
{ }
|
||||
|
||||
# F6.1.56 p3354 A1 Q == 1 (c0606)
|
||||
# F6.1.60 p8002 A1 Q == 1 (c0606)
|
||||
:vcvt^vcvt_56_128_dt Qd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=1))
|
||||
& vcvt_56_128_dt & Qd & Qm
|
||||
{ }
|
||||
|
||||
# F6.1.57 p3356 A1 opc2==100 && size==10 (c1618, c0809)
|
||||
# F6.1.61 p8005 A1 opc2==100 && size==10 (c1618, c0809)
|
||||
:vcvt^COND^".u32.f32" Sd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10))
|
||||
& COND & Sd & Sm
|
||||
{ build COND; Sd = trunc(Sm); }
|
||||
{ build COND; Sd = zext(Sm f> 0) * (trunc(Sm)); }
|
||||
|
||||
# F6.1.57 p3356 A1 opc2==101 && size==10 (c1618, c0809)
|
||||
# F6.1.61 p8005 A1 opc2==101 && size==10 (c1618, c0809)
|
||||
:vcvt^COND^".s32.f32" Sd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10))
|
||||
& COND & Sd & Sm
|
||||
{ build COND; Sd = trunc(Sm); }
|
||||
{ build COND; Sd = zext(Sm f> 0) * (trunc(Sm)); }
|
||||
|
||||
# F6.1.57 p3356 A1 opc2==100 && size==11 (c1618, c0809)
|
||||
# F6.1.61 p8005 A1 opc2==100 && size==11 (c1618, c0809)
|
||||
:vcvt^COND^".u32.f64" Sd,Dm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11))
|
||||
& COND & Sd & Dm
|
||||
{ build COND; local tmp:8 = trunc(Dm); Sd = tmp:4; }
|
||||
{ build COND; local tmp:8 = zext(Dm f> 0) * (trunc(Dm)); Sd = tmp:4; }
|
||||
|
||||
# F6.1.57 p3356 A1 opc2==101 && size==11 (c1618, c0809)
|
||||
# F6.1.61 p8005 A1 opc2==101 && size==11 (c1618, c0809)
|
||||
:vcvt^COND^".s32.f64" Sd,Dm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11))
|
||||
& COND & Sd & Dm
|
||||
{ build COND; local tmp:8 = trunc(Dm); Sd = tmp:4; }
|
||||
{ build COND; local tmp:8 = zext(Dm f> 0:8) * (trunc(Dm)); Sd = tmp:4; }
|
||||
|
||||
# The rounding mode depends on c0707=0 => FPSCR else ZERO
|
||||
|
||||
|
|
@ -698,14 +556,14 @@ vcvt_58_6432_dt: ".f64.s32"
|
|||
& Dd & Sm
|
||||
{ local tmp:8 = sext(Sm); Dd = int2float(tmp); }
|
||||
|
||||
# F6.1.58 p3359 A1 size == 10 (c0809)
|
||||
# F6.1.62 p8009 A1 size == 10 (c0809)
|
||||
:vcvt^COND^vcvt_58_3232_dt Sd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11100 & thv_c1616=0 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))
|
||||
& COND & vcvt_58_3232_dt & Sd & Sm
|
||||
{ build COND; build vcvt_58_3232_dt; }
|
||||
|
||||
# F6.1.58 p3359 A1 size == 11 (c0809)
|
||||
# F6.1.62 p8009 A1 size == 11 (c0809)
|
||||
:vcvt^COND^vcvt_58_6432_dt Dd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11100 & thv_c1616=0 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))
|
||||
|
|
@ -762,14 +620,14 @@ vcvt_59_64_dt: ".u32.f32"
|
|||
# Should add rounding here, if dt2 is s32 or u32 then rounding is
|
||||
# FPRounding_ZERO otherwise FPROunding_TIEEVEN
|
||||
|
||||
# F6.1.59 p3361 A1 Q = 0 (c0606)
|
||||
# F6.1.63 p8012 A1 Q = 0 (c0606)
|
||||
:vcvt^vcvt_59_32_dt Dd,Dm,vcvt_59_fbits
|
||||
is ((TMode=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c0911=0b111 & c0707=0 & c0404=1 & c0606=0)
|
||||
| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c0911=0b111 & thv_c0707=0 & thv_c0404=1 & thv_c0606=0))
|
||||
& vcvt_59_32_dt & vcvt_59_fbits & Dd & Dm
|
||||
{ }
|
||||
|
||||
# F6.1.59 p3361 A1 Q = 1 (c0606)
|
||||
# F6.1.63 p8012 A1 Q = 1 (c0606)
|
||||
:vcvt^vcvt_59_64_dt Qd,Qm,vcvt_59_fbits
|
||||
is ((TMode=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c0911=0b111 & c0707=0 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c0911=0b111 & thv_c0707=0 & thv_c0404=1 & thv_c0606=1))
|
||||
|
|
@ -867,14 +725,14 @@ vcvt_60_64_dt: ".u32.f64"
|
|||
& Dd & Dd2 & vcvt_60_fbits_built
|
||||
{ Dd = FPToFixed(Dd2, 64:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); }
|
||||
|
||||
# F6.1.60 p3364 A1 op=0/1 sf=10 (c1818, c0809)
|
||||
# F6.1.63 p8012 A1 op=0/1 sf=10 (c1818, c0809)
|
||||
:vcvt^COND^vcvt_60_32_dt Sd,Sd2,vcvt_60_fbits
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1717=1 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c1818 & thv_c0809=0b10))
|
||||
& COND & vcvt_60_fbits & vcvt_60_32_dt & Sd & Sd2
|
||||
{ build COND; build vcvt_60_32_dt; }
|
||||
|
||||
# F6.1.60 p3364 A1 op=0/1 sf=11 (c1818, c0809)
|
||||
# F6.1.63 p8012 A1 op=0/1 sf=11 (c1818, c0809)
|
||||
:vcvt^COND^vcvt_60_64_dt Dd,Dd2,vcvt_60_fbits
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1717=1 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c1818 & thv_c0809=0b11))
|
||||
|
|
@ -911,14 +769,14 @@ vcvt_amnp_simd_128_dt: ".s32" is TMode=1 & thv_c0707=0 & thv_c0809 & vcvt_amnp_s
|
|||
vcvt_amnp_simd_128_dt: ".u32" is TMode=0 & c0707=1 & c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); }
|
||||
vcvt_amnp_simd_128_dt: ".u32" is TMode=1 & thv_c0707=1 & thv_c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); }
|
||||
|
||||
# F6.1.61,64,66,68 p3367,3374,3378,3384 A1 64-bit SIMD vector variant Q = 0 (c0606)
|
||||
# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 64-bit SIMD vector variant Q = 0 (c0606)
|
||||
:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_64_dt^".f32" Dd,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=0))
|
||||
& vcvt_amnp_simd_RM & vcvt_amnp_simd_64_dt & Dd & Dm
|
||||
{ }
|
||||
|
||||
# F6.1.61,64,66,68 p3367,3374,3378,3384 A1 128-bit SIMD vector variant Q = 1(c0606)
|
||||
# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 128-bit SIMD vector variant Q = 1(c0606)
|
||||
:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_128_dt^".f32" Qd,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=1))
|
||||
|
|
@ -952,14 +810,14 @@ vcvt_amnp_fp_d_dt: ".u32" is TMode=1 & thv_c0707=0 & thv_c1617 & vcvt_amnp_fp_RM
|
|||
vcvt_amnp_fp_d_dt: ".s32" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); }
|
||||
vcvt_amnp_fp_d_dt: ".s32" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); }
|
||||
|
||||
# F6.1.62,65,67,69 p3369,3376,3380,3384 Single-precision scalar variant size = 11 (c0809)
|
||||
# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 11 (c0809)
|
||||
:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f32" Sd,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))
|
||||
& vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm
|
||||
{ }
|
||||
|
||||
# F6.1.62,65,67,69 p3369,3376,3380,3384 Double-precision scalar variant size = 10 (c0809)
|
||||
# F6.1.66,70,72,74 p8021,8030,8034,8038 Double-precision scalar variant size = 10 (c0809)
|
||||
:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_d_dt^".f64" Sd,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))
|
||||
|
|
@ -1012,32 +870,32 @@ vcvt_bt1664_op: "t"
|
|||
& Sd & Dm
|
||||
{ tmp:2 = float2float(Dm); Sd = (zext(tmp)<<16) | zext(Sd[0,16]); }
|
||||
|
||||
# F6.1.63 p3371 A1 cases op:sz = 00 (c1616, c0808)
|
||||
# F6.1.71 p3389 A1 cases op:sz = 00 (c1616, c0808)
|
||||
# F6.1.67 p8023 A1 cases op:sz = 00 (c1616, c0808)
|
||||
# F6.1.76 p8044 A1 cases op:sz = 00 (c1616, c0808)
|
||||
:vcvt^vcvt_bt3216_op^COND^".f32.f16" Sd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=0)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=0 & thv_c0808=0))
|
||||
& COND & vcvt_bt3216_op & Sd & Sm
|
||||
{ build COND; build vcvt_bt3216_op; }
|
||||
|
||||
# F6.1.63 p3371 A1 cases op:sz = 01 (c1616, c0808)
|
||||
# F6.1.71 p3389 A1 cases op:sz = 01 (c1616, c0808)
|
||||
# F6.1.67 p8023 A1 cases op:sz = 01 (c1616, c0808)
|
||||
# F6.1.76 p8044 A1 cases op:sz = 01 (c1616, c0808)
|
||||
:vcvt^vcvt_bt6416_op^COND^".f64.f16" Dd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=1)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=0 & thv_c0808=1))
|
||||
& COND & vcvt_bt6416_op & Dd & Sm
|
||||
{ build COND; build vcvt_bt6416_op; }
|
||||
|
||||
# F6.1.63 p3371 A1 cases op:sz = 10 (c1616, c0808)
|
||||
# F6.1.71 p3389 A1 cases op:sz = 10 (c1616, c0808)
|
||||
# F6.1.67 p8023 A1 cases op:sz = 10 (c1616, c0808)
|
||||
# F6.1.76 p8044 A1 cases op:sz = 10 (c1616, c0808)
|
||||
:vcvt^vcvt_bt1632_op^COND^".f16.f32" Sd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=0)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=1 & thv_c0808=0))
|
||||
& COND & vcvt_bt1632_op & Sd & Sm
|
||||
{ build COND; build vcvt_bt1632_op; }
|
||||
|
||||
# F6.1.63 p3371 A1 cases op:sz = 11 (c1616, c0808)
|
||||
# F6.1.71 p3389 A1 cases op:sz = 11 (c1616, c0808)
|
||||
# F6.1.67 p8023 A1 cases op:sz = 11 (c1616, c0808)
|
||||
# F6.1.76 p8044 A1 cases op:sz = 11 (c1616, c0808)
|
||||
:vcvt^vcvt_bt1664_op^COND^".f16.f64" Sd,Dm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=1)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=1 & thv_c0808=1))
|
||||
|
|
@ -1046,28 +904,28 @@ vcvt_bt1664_op: "t"
|
|||
|
||||
# vcvtr
|
||||
|
||||
# F6.1.70 p3386 A1 case opc2=100 size=10 (c1618, c0809)
|
||||
# F6.1.75 p8040 A1 case opc2=100 size=10 (c1618, c0809)
|
||||
:vcvtr^COND^".u32.f32" Sd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b100 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10))
|
||||
& COND & Sd & Sm
|
||||
{ build COND; Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, $(FPSCR_RMODE)); }
|
||||
|
||||
# F6.1.70 p3386 A1 case opc2=101 size=10
|
||||
# F6.1.75 p8040 A1 case opc2=101 size=10
|
||||
:vcvtr^COND^".s32.f32" Sd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b101 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10))
|
||||
& COND & Sd & Sm
|
||||
{ build COND; Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, $(FPSCR_RMODE)); }
|
||||
|
||||
# F6.1.70 p3386 A1 case opc2=100 size=11
|
||||
# F6.1.75 p8040 A1 case opc2=100 size=11
|
||||
:vcvtr^COND^".u32.f64" Sd,Dm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b100 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11))
|
||||
& COND & Sd & Dm
|
||||
{ build COND; Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, $(FPSCR_RMODE)); }
|
||||
|
||||
# F6.1.70 p3386 A1 case opc2=101 size=11
|
||||
# F6.1.75 p8040 A1 case opc2=101 size=11
|
||||
:vcvtr^COND^".s32.f64" Sd,Dm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b101 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11))
|
||||
|
|
@ -1090,98 +948,98 @@ define pcodeop FPMaxNum;
|
|||
|
||||
define pcodeop FPMinNum;
|
||||
|
||||
# F6.1.101 p3471 A1/T1 Q = 0 (c0606)
|
||||
# F6.1.117 p8178 A1/T1 Q = 0 (c0606)
|
||||
:vmaxnm^".f32" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMaxNum(Dn, Dm); }
|
||||
|
||||
# F6.1.101 p3471 A1/T1 Q = 1 (c0606)
|
||||
# F6.1.117 p8178 A1/T1 Q = 1 (c0606)
|
||||
:vmaxnm^".f32" Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
|
||||
& Qd & Qn & Qm
|
||||
{ Qd = FPMaxNum(Qn, Qm); }
|
||||
|
||||
# F6.1.101 p3471 A1/T1 Q = 0 (c0606)
|
||||
# F6.1.117 p8178 A1/T1 Q = 0 (c0606)
|
||||
:vmaxnm^".f16" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMaxNum(Dn, Dm); }
|
||||
|
||||
# F6.1.101 p3471 A1/T1 Q = 1 (c0606)
|
||||
# F6.1.117 p8178 A1/T1 Q = 1 (c0606)
|
||||
:vmaxnm^".f16" Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
|
||||
& Qd & Qn & Qm
|
||||
{ Qd = FPMaxNum(Qn, Qm); }
|
||||
|
||||
# F6.1.101 p3471 A2/T2 size = 01 (c0809)
|
||||
# F6.1.117 p8178 A2/T2 size = 01 (c0809)
|
||||
:vmaxnm^".f16" Sd,Sn,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b01)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b01))
|
||||
& Sd & Sn & Sm
|
||||
{ Sd = FPMaxNum(Sn, Sm); }
|
||||
|
||||
# F6.1.101 p3471 A2/T2 size = 10 (c0809)
|
||||
# F6.1.117 p8178 A2/T2 size = 10 (c0809)
|
||||
:vmaxnm^".f32" Sd,Sn,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10))
|
||||
& Sd & Sn & Sm
|
||||
{ Sd = FPMaxNum(Sn, Sm); }
|
||||
|
||||
# F6.1.101 p3471 A2/T2 size = 11 (c0809)
|
||||
# F6.1.117 p8178 A2/T2 size = 11 (c0809)
|
||||
:vmaxnm^".f64" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMaxNum(Dn, Dm); }
|
||||
|
||||
# F6.1.104 p3478 A1/T1 Q = 0 (c0606)
|
||||
# F6.1.120 p8178 A1/T1 Q = 0 (c0606)
|
||||
:vminnm^".f32" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMinNum(Dn, Dm); }
|
||||
|
||||
# F6.1.104 p3478 A1/T1 Q = 1 (c0606)
|
||||
# F6.1.120 p8178 A1/T1 Q = 1 (c0606)
|
||||
:vminnm^".f32" Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
|
||||
& Qd & Qn & Qm
|
||||
{ Qd = FPMinNum(Qn, Qm); }
|
||||
|
||||
# F6.1.104 p3478 A1/T1 Q = 0 (c0606)
|
||||
# F6.1.120 p8178 A1/T1 Q = 0 (c0606)
|
||||
:vminnm^".f16" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=0)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
|
||||
& Dd & Dn & Dm
|
||||
{ Dd = FPMinNum(Dn, Dm); }
|
||||
|
||||
# F6.1.104 p3478 A1/T1 Q = 1 (c0606)
|
||||
# F6.1.120 p8178 A1/T1 Q = 1 (c0606)
|
||||
:vminnm^".f16" Qd,Qn,Qm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=1)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
|
||||
& Qd & Qn & Qm
|
||||
{ Qd = FPMinNum(Qn, Qm); }
|
||||
|
||||
# F6.1.104 p3478 A2/T2 size = 01 (c0809)
|
||||
# F6.1.120 p8178 A2/T2 size = 01 (c0809)
|
||||
:vminnm^".f16" Sd,Sn,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01))
|
||||
& Sd & Sn & Sm
|
||||
{ Sd = FPMinNum(Sn, Sm); }
|
||||
|
||||
# F6.1.104 p3478 A2/T2 size = 10 (c0809)
|
||||
# F6.1.120 p8178 A2/T2 size = 10 (c0809)
|
||||
:vminnm^".f32" Sd,Sn,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))
|
||||
& Sd & Sn & Sm
|
||||
{ Sd = FPMinNum(Sn, Sm); }
|
||||
|
||||
# F6.1.104 p3478 A2/T2 size = 11 (c0809)
|
||||
# F6.1.120 p8178 A2/T2 size = 11 (c0809)
|
||||
:vminnm^".f64" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))
|
||||
|
|
@ -1231,14 +1089,14 @@ vmull_dt: ".p64"
|
|||
| (TMode=1 & thv_c0909=1 & thv_c2828=0 & thv_c2021=0b10))
|
||||
{ }
|
||||
|
||||
# F6.1.130 p3537 VMULL (-integer and +polynomial) op=1 (c0909) (with condition U!=1 and size!=0b11 and size!=01)
|
||||
# F6.1.149 p8266 VMULL (-integer and +polynomial) op=1 (c0909) (with condition U!=1 and size!=0b11 and size!=01)
|
||||
:vmull^vmull_dt Qd,Dn,Dm
|
||||
is ((TMode=0 & c2531=0b1111001 & c2424=0 & c2323=1 & ( c2121 & c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=1)
|
||||
| (TMode=1 & thv_c2931=0b111 & thv_c2828=0 & thv_c2327=0b11111 & (thv_c2121 & thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=1))
|
||||
& vmull_dt & Qd & Dn & Dm
|
||||
{ Qd = PolynomialMult(Dn, Dm); }
|
||||
|
||||
# F6.1.130 p3537 VMULL (+integer and -polynomial) op=0 (c0909) (with condition size!=0b11)
|
||||
# F6.1.149 p8266 VMULL (+integer and -polynomial) op=0 (c0909) (with condition size!=0b11)
|
||||
:vmull^vmull_dt Qd,Dn,Dm
|
||||
is ((TMode=0 & c2531=0b1111001 & c2424 & c2323=1 & ( c2121=0 | c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=0)
|
||||
| (TMode=1 & thv_c2931=0b111 & thv_c2828 & thv_c2327=0b11111 & (thv_c2121=0 | thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=0))
|
||||
|
|
@ -1307,14 +1165,14 @@ vrint_simd_ixf:
|
|||
{ }
|
||||
|
||||
|
||||
# F6.1.178,180,182,184,187,189 p3646,3650,3654,3658,3664,3668 Q = 0 (c0606)
|
||||
# F6.1.199,201,203,205,208,210 p8396,8400,8404,8408,8414,8420 Q = 0 (c0606)
|
||||
:vrint^vrint_simd_RM^".f32" Dd,Dm
|
||||
is ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & (( c0707=0 & c0909=0) | ( c0707=1 & c0909=1) | ( c0707=1 & c0909=0)) & c0404=0 & c0606=0)
|
||||
| (TMode=1 & thv_c2331=0b111111111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c1011=0b01 & ((thv_c0707=0 & thv_c0909=0) | (thv_c0707=1 & thv_c0909=1) | (thv_c0707=1 & thv_c0909=0)) & thv_c0404=0 & thv_c0606=0))
|
||||
& vrint_simd_RM & vrint_simd_exact & vrint_simd_ixf & Dd & Dm
|
||||
{ Dd = FPRoundInt(Dm, 32:1, vrint_simd_RM, 0:1); build vrint_simd_ixf; }
|
||||
|
||||
# F6.1.178,180,182,184,187,189 p3646,3650,3654,3658,3664,3668 Q = 1 (c0606)
|
||||
# F6.1.199,201,203,205,208,210 p8396,8400,8404,8408,8414,8420 Q = 1 (c0606)
|
||||
:vrint^vrint_simd_RM^".f32" Qd,Qm
|
||||
is ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & c0404=0 & c0606=1)
|
||||
| (TMode=1 & thv_c2331=0b111111111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c1011=0b01 & thv_c0404=0 & thv_c0606=1))
|
||||
|
|
@ -1341,14 +1199,14 @@ vrint_fp_RM: "p"
|
|||
| (TMode=1 & thv_c1617=0b10))
|
||||
{ export $(FPRounding_POSINF); }
|
||||
|
||||
# F6.1.179,181,183,185 p3648,3652,3656,3660 size = 10 (c0809)
|
||||
# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 10 (c0809)
|
||||
:vrint^vrint_fp_RM^".f32" Sd,Sm
|
||||
is ((TMode=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b10))
|
||||
& vrint_fp_RM & Sd & Sm
|
||||
{ Sd = FPRoundInt(Sm, 32:1, vrint_fp_RM, 0:1); }
|
||||
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# F6.1.179,181,183,185 p3648,3652,3656,3660 size = 11 (c0809)
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# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 11 (c0809)
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:vrint^vrint_fp_RM^".f64" Dd,Dm
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is ((TMode=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b11))
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|
|
@ -1392,14 +1250,14 @@ vrint_rxz_ixf:
|
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| (TMode=1 & (thv_c1616=0 | thv_c0707=1)))
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{ }
|
||||
|
||||
# F6.1.186,188,190 p3662,3666,3670 A1 size = 10 (c0809)
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# F6.1.207,209,211 p8412,8416,8420 A1 size = 10 (c0809)
|
||||
:vrint^vrint_rxz_RM^COND^".f32" Sd,Sm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b110 & thv_c1718=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & ((thv_c1616=0) | (thv_c1616=1 & thv_c0707=0)) & thv_c0809=0b10))
|
||||
& vrint_rxz_RM & vrint_rxz_exact & vrint_rxz_ixf & COND & Sd & Sm
|
||||
{ build COND; Sd = FPRoundInt(Sm, 32:1, vrint_rxz_RM, vrint_rxz_exact); build vrint_rxz_ixf; }
|
||||
|
||||
# F6.1.186,188,190 p3662,3666,3670 A1 size = 11 (c0809)
|
||||
# F6.1.207,209,211 p8412,8416,8420 A1 size = 11 (c0809)
|
||||
:vrint^vrint_rxz_RM^COND^".f64" Dd,Dm
|
||||
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b110 & thv_c1718=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & ((thv_c1616=0) | (thv_c1616=1 & thv_c0707=0)) & thv_c0809=0b11))
|
||||
|
|
@ -1426,14 +1284,14 @@ vselcond: "vs"
|
|||
| (TMode=1 & thv_c2021=0b01))
|
||||
{ tmp:1 = OV; export tmp; }
|
||||
|
||||
# F6.1.200 p3690 A1/T1 size = 11 doubleprec (c0809)
|
||||
# F6.1.223 p8447 A1/T1 size = 11 doubleprec (c0809)
|
||||
:vsel^vselcond^".f64" Dd,Dn,Dm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11))
|
||||
& vselcond & Dn & Dd & Dm
|
||||
{ Dd = zext(vselcond != 0) * Dn + zext(vselcond == 0) * Dm; }
|
||||
|
||||
# F6.1.200 p3690 A1/T1 size = 10 singleprec (c0809)
|
||||
# F6.1.223 p8447 A1/T1 size = 10 singleprec (c0809)
|
||||
:vsel^vselcond".f32" Sd,Sn,Sm
|
||||
is ((TMode=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10)
|
||||
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10))
|
||||
|
|
|
|||
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